//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module OBIS_DSIF(
   input                         OBSI_RESET,

   input                         OBSI_SYSCLK77,
   input                         OBSI_SYSFP77,
 

   output[2:0]                   DSIF_OUT_SECTOR_ADDR,
   output[4:0]                   DSIF_OUT_BYTE_ADDR,
   input[7:0]                    DSIF_IN_DATA_0,
   input[7:0]                    DSIF_IN_DATA_1,
   input[7:0]                    DSIF_IN_DATA_2,
   input[7:0]                    DSIF_IN_DATA_3,

   output reg                    OBSI_TXD
    );


reg[13:0]                        DTRD_FMCNT9720;
reg[7:0]                         DTRD_E1_CNT256;
reg[2:0]                         DTRD_SECTOR_ADDR;

reg[13:0]                        DTRD_RL1_FMCNT, DTRD_RL2_FMCNT;
wire[13:0]                       DTRD_OUT_FMCNT9720;
wire[7:0]                        DTRD_OUT_DATA_0, DTRD_OUT_DATA_1, DTRD_OUT_DATA_2, DTRD_OUT_DATA_3;


reg[7:0]                         BSEL_BYTE_DATA;
wire[7:0]                        BSEL_BYTE_0;






always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      DTRD_FMCNT9720[13:0]                       <= 14'd0;
   else begin
      if ( OBSI_SYSFP77==1'b1 )
         DTRD_FMCNT9720[13:0]                    <= 14'd1;
      else if ( DTRD_FMCNT9720[13:0]==14'd9719 )
         DTRD_FMCNT9720[13:0]                    <= 14'd0;
      else
         DTRD_FMCNT9720[13:0]                    <= DTRD_FMCNT9720[13:0] +14'd1;
   end
end

always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      DTRD_E1_CNT256[7:0]                        <= 8'd0;
   else begin
      if ( DTRD_FMCNT9720[13:0]==14'd191 )
         DTRD_E1_CNT256[7:0]                     <= 8'd0;
      else if ( DTRD_FMCNT9720[1:0]==2'd3 )
         DTRD_E1_CNT256[7:0]                     <= DTRD_E1_CNT256[7:0] +8'd1;
   end
end
always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      DTRD_SECTOR_ADDR[2:0]                      <= 3'd0;
   else begin
      if ( DTRD_FMCNT9720[13:0]==14'd9719 )
         DTRD_SECTOR_ADDR[2:0]                   <= DTRD_SECTOR_ADDR +3'd1;
   end
end

  assign DSIF_OUT_SECTOR_ADDR[2:0]         = DTRD_SECTOR_ADDR[2:0];
  assign DSIF_OUT_BYTE_ADDR[4:0]           = DTRD_E1_CNT256[7:3];


always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 ) begin
      DTRD_RL1_FMCNT[13:0]                <= 14'd0;
      DTRD_RL2_FMCNT[13:0]                <= 14'd0;
   end
   else begin
      DTRD_RL1_FMCNT[13:0]                <= DTRD_FMCNT9720[13:0];
      DTRD_RL2_FMCNT[13:0]                <= DTRD_RL1_FMCNT[13:0];
   end
end





  assign DTRD_OUT_FMCNT9720[13:0]              = DTRD_RL2_FMCNT[13:0];
  assign DTRD_OUT_DATA_0[7:0]                  = DSIF_IN_DATA_0[7:0];
  assign DTRD_OUT_DATA_1[7:0]                  = DSIF_IN_DATA_1[7:0];
  assign DTRD_OUT_DATA_2[7:0]                  = DSIF_IN_DATA_2[7:0];
  assign DTRD_OUT_DATA_3[7:0]                  = DSIF_IN_DATA_3[7:0];



always @( DTRD_OUT_FMCNT9720 or DTRD_OUT_DATA_0 or DTRD_OUT_DATA_1 or DTRD_OUT_DATA_2 or DTRD_OUT_DATA_3) begin
   if ( DTRD_OUT_FMCNT9720[13:0] < 14'd96 )
      BSEL_BYTE_DATA[7:0]                  <= 8'hF6;
   else if ( DTRD_OUT_FMCNT9720[13:0] < 14'd192 && DTRD_OUT_FMCNT9720[13:0] >=96 )
      BSEL_BYTE_DATA[7:0]                  <= 8'h28;
   else if ( DTRD_OUT_FMCNT9720[13:0]>=14'd192 && DTRD_OUT_FMCNT9720[13:0]<(14'd192 + 14'd1024) )
      BSEL_BYTE_DATA[7:0]                 <= DTRD_OUT_DATA_0[7:0];
   else if ( DTRD_OUT_FMCNT9720[13:0]>=(14'd192 + 14'd1024) && DTRD_OUT_FMCNT9720[13:0]<(14'd192 + 14'd2048) )
      BSEL_BYTE_DATA[7:0]                 <= DTRD_OUT_DATA_1[7:0];
   else if ( DTRD_OUT_FMCNT9720[13:0]>=(14'd192 + 14'd2048) && DTRD_OUT_FMCNT9720[13:0]<(14'd192 + 14'd3072) )
      BSEL_BYTE_DATA[7:0]                 <= DTRD_OUT_DATA_2[7:0];
   else if ( DTRD_OUT_FMCNT9720[13:0]>=(14'd192 + 14'd3072) && DTRD_OUT_FMCNT9720[13:0]<(14'd192 + 14'd4096) )
      BSEL_BYTE_DATA[7:0]                 <= DTRD_OUT_DATA_3[7:0];
   else
      BSEL_BYTE_DATA[7:0]                 <= 8'h55;
end

always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      OBSI_TXD                         <= 1'b0;
   else begin
      case ( DTRD_OUT_FMCNT9720[4:2] )
      3'd0: OBSI_TXD                   <= BSEL_BYTE_DATA[7];
      3'd1: OBSI_TXD                   <= BSEL_BYTE_DATA[6];
      3'd2: OBSI_TXD                   <= BSEL_BYTE_DATA[5];
      3'd3: OBSI_TXD                   <= BSEL_BYTE_DATA[4];
      3'd4: OBSI_TXD                   <= BSEL_BYTE_DATA[3];
      3'd5: OBSI_TXD                   <= BSEL_BYTE_DATA[2];
      3'd6: OBSI_TXD                   <= BSEL_BYTE_DATA[1];
      3'd7: OBSI_TXD                   <= BSEL_BYTE_DATA[0];
      default: ;
      endcase
   end
end

endmodule


